When high-speed and low voltage swing data transfer is needed, differential signaling (also commonly referred to as double ended signals) is perhaps the most robust and promising signaling concept. Differential signaling can add an additional measure of noise immunity due to the fact that the transmitted signal is carried on two conductors and is the difference of the two signals on the two conductors. Current mode logic (CML), a design technique commonly used in high speed signaling applications such as high-speed data communication systems, communications chips and routers, uses differential signaling.
Current-mode-logic (CML) circuits have been widely used in high-speed data communication systems due largely in part to improved switching speeds when compared with voltage-mode-logic circuits. CML circuits can operate with low signal voltages and higher operating frequencies at lower supply voltages than static CMOS circuits. CML is also widely used in high-speed applications due to its relatively low power consumption and low supply voltage when compared to other types of logic designs, such as emitter coupled logic (ECL). CML is also considerably faster than CMOS due to its lower voltage swings.
CML has an additional advantage over other high-speed forms of logic such as logic using Gallium Arsenide (GaAs) in that CML can be fabricated using the same fabrication lines as the widely used CMOS circuits, thus allowing CML circuits to be created on high-technology fabrication lines without requiring a significant outlay of money to create a special fabrication line. Additionally, CML logic may cohabitate with CMOS logic on the same integrated circuit. Therefore, such hybrid circuits can combine the high-speed aspects of CML logic and the low power requirements of CMOS logic.
While CML has been widely used in high-speed data communication systems, even with current state-of-the-art CMOS technology, it is still challenging to design CML based logic circuits for today's higher speed data communication applications, e.g., for 10 Gb/s (Giga-bits per second) and beyond data communications. Various approaches have been proposed for increasing the switching speeds of CML based logic circuits, the speeds of which are generally limited by parasitic capacitances as well as loading capacitances present in the circuits. Examples of such techniques include spiral inductor shunt peaking or active inductor shunt peaking. The use of a conventional spiral inductor for shunt peaking, however, occupies excessive amounts of chip area. CML circuits with conventional active inductor shunt peaking require additional on-chip high voltage generation circuitry, which makes the design more complex and also consumes chip area.
Therefore, there remains a need for a technique for enhancing switching speeds in CML circuit, and particularly for techniques that conserve chip area and/or that do not require additional high voltage generation circuitry.